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Classes | Public Member Functions | Protected Member Functions | Protected Attributes

c6805 Class Reference

#include <cpu.h>

Inheritance diagram for c6805:

List of all members.

Classes

struct  CC

Public Member Functions

 c6805 (void)
virtual ~c6805 ()

Protected Member Functions

int Run (int max_count)
void AddBreakpoint (unsigned short addr)
void ClearBreakpoints (void)
bool AddMapper (cMap *map, unsigned short start, int size, unsigned char seg=0)
void ResetMapper (void)
unsigned char Get (unsigned short ea) const
unsigned char Get (unsigned char seg, unsigned short ea) const
void Set (unsigned short ea, unsigned char val)
void Set (unsigned char seg, unsigned short ea, unsigned char val)
void GetMem (unsigned short addr, unsigned char *data, int len, unsigned char seg=0) const
void SetMem (unsigned short addr, const unsigned char *data, int len, unsigned char seg=0)
void ForceSet (unsigned short ea, unsigned char val, bool ro)
void SetSp (unsigned short SpHi, unsigned short SpLow)
void SetPc (unsigned short addr, unsigned char seg=0)
unsigned short GetPc (void) const
void PopPc (void)
void PopCr (void)
void Push (unsigned char c)
void ResetCycles (void)
void AddCycles (unsigned int num)
unsigned int Cycles (void)
void RaiseException (int num)
void ClearExceptions (void)
void SetExptBase (unsigned short base)
void DisableTimers (int num)
virtual void Stepper (void)=0
virtual void WriteHandler (unsigned char seg, unsigned short ea, unsigned char &op)
virtual void ReadHandler (unsigned char seg, unsigned short ea, unsigned char &op)
virtual void TimerHandler (unsigned int num)
char * PADDR (unsigned char s, unsigned short ea)

Protected Attributes

unsigned char a
unsigned char x
unsigned char y
unsigned char cr
unsigned char dr
struct c6805::CC cc
bool hasReadHandler
bool hasWriteHandler
cLineBuff * loglb

Detailed Description

Definition at line 102 of file cpu.h.

Constructor & Destructor Documentation

c6805::c6805 ( void  )

Definition at line 143 of file cpu.c.

References a, c6805::CC::c, cc, ClearBreakpoints(), ClearExceptions(), cr, dr, c6805::CC::h, hasReadHandler, hasWriteHandler, c6805::CC::i, loglb, c6805::CC::n, ResetCycles(), c6805::CC::v, x, y, and c6805::CC::z.

{
  cc.c=0; cc.z=0; cc.n=0; cc.i=0; cc.h=0; cc.v=1;
  pc=0; a=0; x=0; y=0; cr=dr=0; sp=spHi=0x100; spLow=0xC0;
  hasReadHandler=hasWriteHandler=false;
  exptBase=0x4000;
  ResetCycles();
  ClearExceptions();
  ClearBreakpoints();
  InitMapper();
  memset(stats,0,sizeof(stats));
  loglb=new cLineBuff(128);
}
c6805::~c6805 ( ) [virtual]

Definition at line 157 of file cpu.c.

References i, j, L_SYS_CPUSTATS, LOG, loglb, PRINTF, and x.

{
  if(LOG(L_SYS_CPUSTATS)) {
    int i, j, sort[256];
    for(i=0; i<256; i++) sort[i]=i;
    for(i=0; i<256; i++)
      for(j=0; j<255; j++)
        if(stats[sort[j]]<stats[sort[j+1]]) {
          int x=sort[j]; sort[j]=sort[j+1]; sort[j+1]=x;
          }
    PRINTF(L_SYS_CPUSTATS,"opcode statistics");
    for(i=0; i<256; i++)
      if((j=stats[sort[i]])) PRINTF(L_SYS_CPUSTATS,"opcode %02x: %d",sort[i],j);
    }
  ClearMapper();
  delete loglb;
}

Member Function Documentation

void c6805::AddBreakpoint ( unsigned short  addr) [protected]

Definition at line 285 of file cpu.c.

References L_SYS_EMU, MAX_BREAKPOINTS, and PRINTF.

Referenced by cN2Prov0101::Algo(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cEmu::Init(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0101::RomInit(), cN2Prov0501::RunEmu(), and cN2Prov0101::RunEmu().

{
  if(numBp<MAX_BREAKPOINTS) {
    bp[numBp++]=addr;
    PRINTF(L_SYS_EMU,"6805: setting breakpoint at 0x%04x",addr);
    }
  else PRINTF(L_SYS_EMU,"6805: too many breakpoints");
}
void c6805::AddCycles ( unsigned int  num) [protected]

Definition at line 300 of file cpu.c.

References TimerHandler().

Referenced by cN2Prov0501::AddMapCycles(), cN2Prov0101::AddMapCycles(), and Run().

{
  if(num>0) {
    clockcycles+=num;
    if(timerDisable>0) {
      timerDisable-=num;
      if(timerDisable<0) timerDisable=0;
      }
    if(!timerDisable)
      TimerHandler(num);
    }
}
bool c6805::AddMapper ( cMap *  map,
unsigned short  start,
int  size,
unsigned char  seg = 0 
) [protected]

Definition at line 175 of file cpu.c.

References cMap::IsFine(), L_SYS_EMU, loglb, cMap::loglb, MAX_MAPPER, PAGEOFF, and PRINTF.

Referenced by cEmu::AddEeprom(), cEmu::AddRom(), cN2Emu::Init(), cN2Prov0501::RomInit(), and cN2Prov0101::RomInit().

{
  if(map && map->IsFine()) {
    if(nextMapper<MAX_MAPPER) {
      map->loglb=loglb;
      mapper[nextMapper]=map;
      memset(&mapMap[start+PAGEOFF(start,seg)],nextMapper,size);
      nextMapper++;
      return true;
      }
    else PRINTF(L_SYS_EMU,"6805: too many mappers");
    }
  else PRINTF(L_SYS_EMU,"6805: mapper not ready (start=%02x:%04x size=%04x)",seg,start,size);
  delete map;
  return false;
}
void c6805::ClearBreakpoints ( void  ) [protected]

Definition at line 294 of file cpu.c.

Referenced by cN2Prov0101::Algo(), c6805(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cEmu::Init(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0101::RomInit(), cN2Prov0501::RunEmu(), and cN2Prov0101::RunEmu().

{
  numBp=0;
  memset(bp,0,sizeof(bp));
}
void c6805::ClearExceptions ( void  ) [protected]

Definition at line 326 of file cpu.c.

References EXPT_MAX, and i.

Referenced by c6805(), and SetPc().

{
  exptPending=false; exptReady=true; timerDisable=0;
  for(int i=0; i<EXPT_MAX; i++) expt[i]=false;
}
unsigned int c6805::Cycles ( void  ) [inline, protected]

Definition at line 154 of file cpu.h.

Referenced by cN2Prov0501::CpuCycles(), cN2Prov0101::CpuCycles(), and cN2Prov0101::ReadHandler().

{ return clockcycles; }
void c6805::DisableTimers ( int  num) [protected]

Definition at line 332 of file cpu.c.

Referenced by cN2Prov0101::TimerHandler().

{
  timerDisable=num;
}
void c6805::ForceSet ( unsigned short  ea,
unsigned char  val,
bool  ro 
) [protected]

Definition at line 240 of file cpu.c.

References Set().

Referenced by cEmuRom10Core::CoreInitSetup(), cEmuRom3Core::CoreInitSetup(), and cEmu::Init().

{
  mapMap[ea]=0;                 // reset to RAM map
  Set(0,ea,val);                // set value
  if(ro) mapMap[ea]|=0x80;      // protect byte
}
unsigned char c6805::Get ( unsigned short  ea) const [protected]

Definition at line 216 of file cpu.c.

References cr, cMap::Get(), and PAGEOFF.

Referenced by GetMem(), cEmu::GetPkKeys(), cEmuRom10::MathMapHandler(), cN2Prov4101::ProcessBx(), cEmuRom10Core::ReadHandler(), cEmuRom3Core::ReadHandler(), Run(), cN2Prov0101::Stepper(), cN2Prov4101::WriteHandler(), and cEmuRom10Core::WriteHandler().

{
  return mapper[mapMap[ea+PAGEOFF(ea,cr)]&0x7f]->Get(ea);
}
unsigned char c6805::Get ( unsigned char  seg,
unsigned short  ea 
) const [protected]

Definition at line 221 of file cpu.c.

References cMap::Get(), and PAGEOFF.

{
  return mapper[mapMap[ea+PAGEOFF(ea,seg)]&0x7f]->Get(ea);
}
void c6805::GetMem ( unsigned short  addr,
unsigned char *  data,
int  len,
unsigned char  seg = 0 
) const [protected]

Definition at line 252 of file cpu.c.

References Get().

Referenced by cN2Prov0101::Algo(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cEmuRom10::MathMapHandler(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0501::RunEmu(), and cN2Prov0101::RunEmu().

{
  while(len>0) { *data++=Get(seg,addr++); len--; }
}
unsigned short c6805::GetPc ( void  ) const [inline, protected]

Definition at line 148 of file cpu.h.

Referenced by cN2Prov0101::Algo(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0101::RomInit(), cN2Prov0501::RunEmu(), cN2Prov0101::RunEmu(), cN2Prov0101::Stepper(), and cN2Prov0101::TimerHandler().

{ return pc; }
char * c6805::PADDR ( unsigned char  s,
unsigned short  ea 
) [protected]

Definition at line 410 of file cpu.c.

Referenced by Run().

{
  snprintf(addrBuff,sizeof(addrBuff),((ea&0x8000) && s>0)?"%2$x:%1$04x":"%04x",ea,s);
  return addrBuff;
}
void c6805::PopCr ( void  ) [protected]

Definition at line 275 of file cpu.c.

References cr.

{
  cr=pop();
}
void c6805::PopPc ( void  ) [protected]

Definition at line 270 of file cpu.c.

Referenced by cEmu::GetOpKeys(), and cN2Prov4101::ProcessBx().

{
  poppc();
}
void c6805::Push ( unsigned char  c) [protected]

Definition at line 280 of file cpu.c.

Referenced by cN2Prov0101::ProcessEx().

{
  push(c);
}
void c6805::RaiseException ( int  num) [protected]

Definition at line 318 of file cpu.c.

References EXPT_MAX.

Referenced by cN2Prov0101::TimerHandler().

{
  if(num<EXPT_MAX) {
    exptPending=true;
    expt[num]=true;
    }
}
virtual void c6805::ReadHandler ( unsigned char  seg,
unsigned short  ea,
unsigned char &  op 
) [inline, protected, virtual]

Reimplemented in cEmuRom3Core, cEmuRom10Core, and cN2Prov0101.

Definition at line 161 of file cpu.h.

Referenced by Run().

{}
void c6805::ResetCycles ( void  ) [protected]

Definition at line 313 of file cpu.c.

Referenced by c6805(), and SetPc().

{
  clockcycles=0;
}
void c6805::ResetMapper ( void  ) [protected]

Definition at line 192 of file cpu.c.

Referenced by cN2Emu::Init().

{
  ClearMapper(); InitMapper();
}
int c6805::Run ( int  max_count) [protected]

Definition at line 416 of file cpu.c.

References a, AddCycles(), bitset, c6805::CC::c, cc, CCLOGLBPUT, count, cr, dr, EXPT_MAX, flags, Get(), c6805::CC::h, hasReadHandler, HILO, HILOS, c6805::CC::i, i, L_SYS_DISASM, L_SYS_DISASM80, L_SYS_EMU, LOG, loglb, LOGLBPUT, c6805::CC::n, PADDR(), PAGEOFF, PRINTF, PUTLB, ReadHandler(), Set(), Stepper(), c6805::CC::v, x, y, and c6805::CC::z.

Referenced by cN2Prov0101::Algo(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cEmu::Init(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0101::RomInit(), cN2Prov0501::RunEmu(), and cN2Prov0101::RunEmu().

{
// returns:
// 0 - breakpoint
// 1 - stack overflow
// 2 - instruction counter exeeded
// 3 - unsupported instruction

  bool disAsmHeader=false;
  disAsmLogClass=L_SYS_DISASM;
  if(LOG(L_SYS_DISASM)) doDisAsm=true;
  else {
    doDisAsm=false;
    if(LOG(L_SYS_DISASM80)) disAsmLogClass=L_SYS_DISASM80;
    }

  int count=0;
  while (1) {
    if(exptPending && exptReady) {
      exptPending=false;
      for(int i=0; i<EXPT_MAX; ++i)
        if(expt[i]) {
          exptPending=true; // to force check for another interrupt in next Run pass
          expt[i]=false;
          pushpc(); push(x); push(a); pushc(); cc.i=1;
          pc=exptBase+4*i;
          timerDisable=0;
          break;
          }
      }
    exptReady=!cc.i;
    Stepper();
    if(sp<spLow) {
      PRINTF(L_SYS_EMU,"stack overflow (count=%d)",count);
      return 1;
      }
    if(spHi>spLow && sp>spHi) {
      PRINTF(L_SYS_EMU,"stack underflow (count=%d)",count);
      return 1;
      }
    if(pc>0x0400 && mapMap[pc+PAGEOFF(pc,cr)]==0) {
      PRINTF(L_SYS_EMU,"NX protection at %04x (count=%d)",pc,count);
      return 1;
      }
    count++;

    if(!LOG(L_SYS_DISASM) && LOG(L_SYS_DISASM80)) {
      bool flag=(pc>=0x80 && pc<0x200);
      if(doDisAsm && !flag) PRINTF(disAsmLogClass,"[...]");
      doDisAsm=flag;
      }

    if(doDisAsm && !disAsmHeader) {
      PRINTF(disAsmLogClass,"cr:-pc- aa xx yy dr -sp- VHINZC -mem@pc- -mem@sp- -cycles-");
      disAsmHeader=true;
      }
    CCLOGLBPUT("%02x:%04x %02x %02x %02x %02x %04x %c%c%c%c%c%c %02x%02x%02x%02x %02x%02x%02x%02x %08x ",
               cr,pc,a,x,y,dr,sp,
               cc.v?'V':'.',cc.h?'H':'.',cc.i?'I':'.',cc.n?'N':'.',cc.z?'Z':'.',cc.c?'C':'.',
               Get(pc),Get(pc+1),Get(pc+2),Get(pc+3),Get(sp+1),Get(sp+2),Get(sp+3),Get(sp+4),
               clockcycles);

    unsigned char *ex=&x;
    unsigned short idx=*ex;
    indirect=false;
    bool paged=false, vbra=false;
    unsigned char ins=Get(pc++);
    char xs='X', xi='X';
    int cycles=0;
 
    // check pre-bytes
    switch(ins) {
      case 0x31: // use SP indexed or indirect paged mode (ST19)
        cycles+=2;
        ins=Get(pc++);
        switch(ins) {
          case 0x22: case 0x23: case 0x24: case 0x25:
          case 0x26: case 0x27:
            vbra=true; break;
          case 0x8D:
            cycles++;
            // fall through
          case 0x75:
          case 0xC0: case 0xC1: case 0xC2: case 0xC3:
          case 0xC4: case 0xC5: case 0xC6: case 0xC7:
          case 0xC8: case 0xC9: case 0xCA: case 0xCB:
          case 0xCE: case 0xCF:
          case 0xD0: case 0xD1: case 0xD2: case 0xD3:
          case 0xD4: case 0xD5: case 0xD6: case 0xD7:
          case 0xD8: case 0xD9: case 0xDA: case 0xDB:
          case 0xDE: case 0xDF:
            paged=true; indirect=true; break;
          case 0xE0: case 0xE1: case 0xE2: case 0xE3:
          case 0xE4: case 0xE5: case 0xE6: case 0xE7:
          case 0xE8: case 0xE9: case 0xEA: case 0xEB:
          case 0xEE: case 0xEF:
            idx=sp; xi='S'; break;
          }
        break;
      case 0x32: // use indirect SP indexed or indirect paged Y indexed mode (ST19)
        cycles+=2;
        ins=Get(pc++);
        switch(ins) {
          case 0x22: case 0x23: case 0x24: case 0x25:
          case 0x26: case 0x27:
            vbra=true; indirect=true; break;
          case 0xC3:
          case 0xCE: case 0xCF:
          case 0xD0: case 0xD1: case 0xD2: case 0xD3:
          case 0xD4: case 0xD5: case 0xD6: case 0xD7:
          case 0xD8: case 0xD9: case 0xDA: case 0xDB:
          case 0xDE: case 0xDF:
            paged=true; indirect=true; ex=&y; idx=*ex; xs='Y'; xi='Y'; break;
          case 0xE0: case 0xE1: case 0xE2: case 0xE3:
          case 0xE4: case 0xE5: case 0xE6: case 0xE7:
          case 0xE8: case 0xE9: case 0xEA: case 0xEB:
          case 0xEE: case 0xEF:
            indirect=true; idx=sp; xi='S'; break;
          }
        break;
      case 0x91: // use Y register with indirect addr mode (ST7)
        cycles++;
        indirect=true;
        // fall through
      case 0x90: // use Y register (ST7)
        cycles++;
        ex=&y; idx=*ex; xs='Y'; xi='Y';
        ins=Get(pc++);
        break;
      case 0x92: // use indirect addr mode (ST7)
        cycles+=2;
        indirect=true;
        ins=Get(pc++);
        break;
      }
    cycles+=clock_cycles[ins];
    int readCycles=clock_cycles[ins]>=2 ? 2:0;
    AddCycles(readCycles);

    if(doDisAsm) {
      char str[8];
      if(!vbra) snprintf(str,sizeof(str),ops[ins],xs,xs^1);
      else snprintf(str,sizeof(str),"%s",vops[ins-0x22]);
      LOGLBPUT("%-5s ",str);
      }

    // address decoding
    unsigned short ea=0;
    unsigned char flags=opFlags[ins];
    unsigned char pr=(flags&4) ? dr:cr;
    switch(((flags&8) ? flags:ins)>>4) {
      case 0x2:                 // no or special address mode
      case 0x8:
      case 0x9:
        break;
      case 0xA:                 // immediate
        CCLOGLBPUT("#%02x ",Get(pc));
        ea=pc++; break;
      case 0x3:                 // short
      case 0xB:
        ea=Get(pc++);
        if(!indirect) {         // short direct
          }
        else {                  // short indirect
          CCLOGLBPUT("[%02x] -> ",ea);
          ea=Get(ea);
          }
        CCLOGLBPUT("%02x ",ea);
        break;
      case 0xC:                 // long
        if(!indirect) {         // long direct
          ea=HILO(pc); pc+=2;
          }
        else {                  // long indirect
          if(paged) {
            ea=HILO(pc); pc+=2;
            CCLOGLBPUT("[%s] -> ",PADDR(pr,ea));
            unsigned char s=Get(pr,ea);
            ea=HILOS(pr,ea+1);
            pr=s;
            }
          else {
            ea=Get(pc++);
            CCLOGLBPUT("[%02x] -> ",ea);
            ea=HILO(ea);
            }
          }
        CCLOGLBPUT("%s ",PADDR(pr,ea));
        break;
      case 0xD:                 // long indexed
        if(!indirect) {         // long direct indexed
          ea=HILO(pc); pc+=2;
          CCLOGLBPUT("(%s",PADDR(cr,ea));
          }
        else {                  // long indirect indexed
          if(paged) {
            ea=HILO(pc); pc+=2;
            CCLOGLBPUT("([%s]",PADDR(pr,ea));
            unsigned char s=Get(pr,ea++);
            ea=HILOS(pr,ea);
            pr=s;
            }
          else {
            ea=Get(pc++);
            CCLOGLBPUT("([%02x]",ea);
            ea=HILO(ea);
            }
          CCLOGLBPUT(",%c) -> (%s",xi,PADDR(pr,ea));
          }
        ea+=idx;
        CCLOGLBPUT(",%c) -> %s ",xi,PADDR(pr,ea));
        break;
      case 0x6:                 // short indexed
      case 0xE:
        ea=Get(pc++);
        if(!indirect) {         // short direct indexed
          CCLOGLBPUT("(%02x",ea);
          }
        else {                  // short indirect indexed
          CCLOGLBPUT("([%02x]",ea);
          ea=Get(ea);
          CCLOGLBPUT(",%c) -> (%02x",xi,ea);
          }
        ea+=idx;
        CCLOGLBPUT(",%c) -> %s ",xi,PADDR(pr,ea));
        break;
      case 0x7:                 // indexed
      case 0xF:
        ea=idx;
        CCLOGLBPUT("(%c) -> %s ",xi,PADDR(pr,ea));
        break;
      case 0x4:                 // inherent A
        CCLOGLBPUT("A ");
        break;
      case 0x5:                 // inherent X/Y
        CCLOGLBPUT("%c ",xs);
        break;
      case 0x0:                 // bit
      case 0x1:
        ea=Get(pc++);
        if(!indirect) {
          }
        else {
          CCLOGLBPUT("[%02x] -> ",ea);
          ea=Get(ea);
          indirect=false; // don't use indirect mode in case this is a bit branch
          }
        CCLOGLBPUT("%02x ",ea);
        break;
      }

    // read operant
    unsigned char op=0;
    if(flags & 1) {
      switch(((flags&8) ? flags:ins)>>4) {
        case 0x2:                       // no or special address mode
        case 0x8:
        case 0x9:
          break;
        case 0x3:                       // short
        case 0xB:
        case 0xC:                       // long
        case 0xD:                       // long indexed
        case 0x6:                       // short indexed
        case 0xE:
        case 0x7:                       // indexed
        case 0xF:
        case 0x0:                       // bit
        case 0x1:
          op=Get(pr,ea);
          if(hasReadHandler) ReadHandler(pr,ea,op);
          CCLOGLBPUT("{%02x} ",op);
          break;
        case 0xA:                       // immediate
          op=Get(pr,ea);
          break;
        case 0x4:                       // inherent A
          op=a; break;
        case 0x5:                       // inherent X/Y
          op=*ex; break;
        }
      }

    AddCycles(cycles-readCycles);

    // command decoding
    stats[ins]++;
    switch(ins) {
      case 0xA6: // LDA
      case 0xB6:
      case 0xC6:
      case 0xD6:
      case 0xE6:
      case 0xF6:
        a=op; tst(op); break;
      case 0xAE: // LDX
      case 0xBE:
      case 0xCE:
      case 0xDE:
      case 0xEE:
      case 0xFE:
        *ex=op; tst(op); break;
      case 0xB7: // STA
      case 0xC7:
      case 0xD7:
      case 0xE7:
      case 0xF7:
        op=a; tst(op); break;
      case 0xBF: // STX
      case 0xCF:
      case 0xDF:
      case 0xEF:
      case 0xFF:
        op=*ex; tst(op); break;
      case 0x97: // TAX
        *ex=a; break;
      case 0x9F: // TXA
        a=*ex; break;
      case 0x93: // TYX (ST7)
        if(ex==&x) *ex=y; else *ex=x; break;
      case 0x3D: // TST
      case 0x4D:
      case 0x5D:
      case 0x6D:
      case 0x7D:
        tst(op); break;
      case 0x3F: // CLR
      case 0x4F:
      case 0x5F:
      case 0x6F:
      case 0x7F:
        op=0; tst(0); break;
      case 0x3C: // INC
      case 0x4C:
      case 0x5C:
      case 0x6C:
      case 0x7C:
        op++; cc.v=(op==0x80); tst(op); break;
      case 0x3A: // DEC
      case 0x4A:
      case 0x5A:
      case 0x6A:
      case 0x7A:
        op--; cc.v=(op==0x7f); tst(op); break;
      case 0x33: // COM
      case 0x43:
      case 0x53:
      case 0x63:
      case 0x73:
        op=~op; cc.c=1; tst(op); break;
      case 0x30: // NEG
      case 0x40:
      case 0x50:
      case 0x60:
      case 0x70:
        op=~op+1; cc.c=(op!=0); cc.v=(op==0x80); tst(op); break;
      case 0x42: // MUL
      case 0x52:
        {
        unsigned short res=*ex * a;
        *ex=(res>>8); a=res&0xff; cc.c=0; cc.h=0;
        break;
        }
      case 0xA9: // ADC
      case 0xB9:
      case 0xC9:
      case 0xD9:
      case 0xE9:
      case 0xF9:
        a=add(op,cc.c); break;
      case 0xAB: // ADD
      case 0xBB:
      case 0xCB:
      case 0xDB:
      case 0xEB:
      case 0xFB:
        a=add(op,0); break;
      case 0xA2: // SBC
      case 0xB2:
      case 0xC2:
      case 0xD2:
      case 0xE2:
      case 0xF2:
        a=sub(a,op,cc.c); break;
      case 0xA0: // SUB
      case 0xB0:
      case 0xC0:
      case 0xD0:
      case 0xE0:
      case 0xF0:
        a=sub(a,op,0); break;
      case 0xA1: // CMP
      case 0xB1:
      case 0xC1:
      case 0xD1:
      case 0xE1:
      case 0xF1:
        sub(a,op,0); break;
      case 0xA3: // CPX
      case 0xB3:
      case 0xC3:
      case 0xD3:
      case 0xE3:
      case 0xF3:
        sub(*ex,op,0); break;
      case 0xA4: // AND
      case 0xB4:
      case 0xC4:
      case 0xD4:
      case 0xE4:
      case 0xF4:
        a &= op; tst(a); break;
      case 0xAA: // ORA
      case 0xBA:
      case 0xCA:
      case 0xDA:
      case 0xEA:
      case 0xFA:
        a |= op; tst(a); break;
      case 0xA8: // EOR
      case 0xB8:
      case 0xC8:
      case 0xD8:
      case 0xE8:
      case 0xF8:
        a ^= op; tst(a); break;
      case 0xA5: // BIT
      case 0xB5:
      case 0xC5:
      case 0xD5:
      case 0xE5:
      case 0xF5:
        tst(a & op); break;
      case 0x38: // ASL
      case 0x48:
      case 0x58:
      case 0x68:
      case 0x78:
        op=rollL(op,0); break;
      case 0x39: // ROL
      case 0x49:
      case 0x59:
      case 0x69:
      case 0x79:
        op=rollL(op,cc.c); break;
      case 0x37: // ASR
      case 0x47:
      case 0x57:
      case 0x67:
      case 0x77:
        op=rollR(op,bitset(op,7)); break;
      case 0x34: // LSR
      case 0x44:
      case 0x54:
      case 0x64:
      case 0x74:
        op=rollR(op,0); break;
      case 0x36: // ROR
      case 0x46:
      case 0x56:
      case 0x66:
      case 0x76:
        op=rollR(op,cc.c); break;
      case 0x3E: // SWAP (ST7)
      case 0x4E:
      case 0x5E:
      case 0x6E:
      case 0x7E:
        op=(op<<4)|(op>>4); tst(op); break;
      //case 0x00 ... 0x0F: // BRSET BRCLR
      case 0x00: case 0x01: case 0x02: case 0x03:
      case 0x04: case 0x05: case 0x06: case 0x07:
      case 0x08: case 0x09: case 0x0A: case 0x0B:
      case 0x0C: case 0x0D: case 0x0E: case 0x0F:
        {
        int bit=(ins&0x0F)>>1;
        CCLOGLBPUT(",#%x,",bit);
        cc.c=bitset(op,bit);
        branch((ins&0x01) ? !cc.c:cc.c);
        break;
        }
      //case 0x10 ... 0x1F: // BSET BCLR
      case 0x10: case 0x11: case 0x12: case 0x13:
      case 0x14: case 0x15: case 0x16: case 0x17:
      case 0x18: case 0x19: case 0x1A: case 0x1B:
      case 0x1C: case 0x1D: case 0x1E: case 0x1F:
        {
        int bit=(ins&0x0F)>>1;
        CCLOGLBPUT(",#%x",bit);
        if(ins&0x01) op &= ~(1<<bit);
        else         op |=  (1<<bit);
        break;
        }
      case 0x20: // BRA
        branch(true); break;
      case 0x21: // BRN
        branch(false); break;
      case 0x22: // BHI
        if(vbra) branch(!cc.z && ((cc.n && cc.v) || (!cc.n && !cc.v)));
        else branch(!cc.c && !cc.z);
        break;
      case 0x23: // BLS
        if(vbra) branch(cc.z || (cc.n && !cc.v) || (!cc.n && cc.v));
        else branch( cc.c ||  cc.z);
        break;
      case 0x24: // BCC BHS
        if(vbra) branch((cc.n && cc.v) || (!cc.n && !cc.v));
        else branch(!cc.c);
        break;
      case 0x25: // BCS BLO
        if(vbra) branch((cc.n && !cc.v) || (!cc.n && cc.v));
        else branch( cc.c);
        break;
      case 0x26: // BNE
        if(vbra) branch(!cc.v);
        else branch(!cc.z);
        break;
      case 0x27: // BEQ
        if(vbra) branch(cc.v);
        else branch( cc.z); break;
      case 0x28: // BHCC
        branch(!cc.h); break;
      case 0x29: // BHCS
        branch( cc.h); break;
      case 0x2A: // BPL
        branch(!cc.n); break;
      case 0x2B: // BMI
        branch( cc.n); break;
      case 0x2C: // BMC
        branch(!cc.i); break;
      case 0x2D: // BMS
        branch( cc.i); break;
      case 0xBC: // JMP
      case 0xCC:
      case 0xDC:
      case 0xEC:
      case 0xFC:
        pc=ea; break;
      case 0xAD: // BSR
        pc++; pushpc(); pc--; branch(true); break;
      case 0xBD: // JSR
      case 0xCD:
      case 0xDD:
      case 0xED:
      case 0xFD:
        pushpc(); pc=ea; break;
      case 0x81: // RTS
        poppc(); break;
      case 0x83: // SWI
        pushpc(); push(x); push(a); pushc();
        cc.i=1; pc=HILO(0x1ffc); break;
      case 0x80: // RTI
        popc(); a=pop(); x=pop(); poppc(); break;
      case 0x9C: // RSP
        sp=spHi; break;
      case 0x96: // TSX
        *ex=sp&0xFF; break;
      case 0x94: // TXS (ST7)
        sp=(sp&0xFF00)|*ex; break;
      case 0x9E: // TSA
        a=sp&0xFF; break;
      case 0x95: // TAS (ST7)
        sp=(sp&0xFF00)|a; break;
      case 0x84: // POPA (ST7)
        a=pop(); break;
      case 0x85: // POPX (ST7)
        *ex=pop(); break;
      case 0x86: // POPC (ST7)
        popc(); break;
      case 0x88: // PUSHA (ST7)
        push(a); break;
      case 0x89: // PUSHX (ST7)
        push(*ex); break;
      case 0x8A: // PUSHC (ST7)
        pushc(); break;
      case 0x98: // CLC
        cc.c=0; break;
      case 0x99: // SEC
        cc.c=1; break;
      case 0x9A: // CLI
        cc.i=0; break;
      case 0x9B: // SEI
        cc.i=1; break;
      case 0x9D: // NOP
        break;

      case 0x71: // LDD (ST19)
      case 0x72:
      case 0x75:
        dr=op; break;
      case 0x7B: // TAD (ST19)
        dr=a; break;
      case 0x8B: // TDA (ST19)
        a=dr; break;
      case 0x8C: // TCA (ST19)
        a=cr; break;
      case 0xAC: // PUSHD (ST19)
        push(dr); break;
      case 0xAF: // POPD (ST19)
        dr=pop(); break;
      case 0x87: // PRTS (ST19)
        cr=pop(); poppc(); break;
      case 0x8D: // PJSR (ST19)
        if(paged) {
          ea=HILO(pc); pc+=2;
          CCLOGLBPUT("[%s] -> ",PADDR(cr,ea));
          }
        else {
          ea=pc; pc+=3;
          }
        pr=Get(ea++);
        ea=HILO(ea);
        CCLOGLBPUT("%s ",PADDR(pr,ea));
        pushpc(); push(cr); cr=pr; pc=ea; break;

      case 0x90: // pre-bytes
      case 0x91:
      case 0x92:
      case 0x31:
      case 0x32:
        PRINTF(L_SYS_EMU,"pre-byte %02x in command decoding (count=%d)",ins,count);
        loglb->cLineBuff::Flush();
        return 3;
      default:
        PRINTF(L_SYS_EMU,"unsupported instruction 0x%02x (count=%d)",ins,count);
        loglb->cLineBuff::Flush();
        return 3;
      }

    // write operant
    if(flags & 2) {
      switch(((flags&8) ? flags:ins)>>4) {
        case 0x2:                       // no or special address mode
        case 0x8:
        case 0x9:
          break;
        case 0xA:                       // immediate
        case 0x3:                       // short
        case 0xB:
        case 0xC:                       // long
        case 0xD:                       // long indexed
        case 0x6:                       // short indexed
        case 0xE:
        case 0x7:                       // indexed
        case 0xF:
        case 0x0:                       // bit
        case 0x1:
          Set(ea,op); break;
        case 0x4:                       // inherent A
          a=op; break;
        case 0x5:                       // inherent X/Y
          *ex=op; break;
        }
      }
    if(doDisAsm) PUTLB(disAsmLogClass,loglb);
    else loglb->cLineBuff::Flush();

    for(int i=numBp-1 ; i>=0 ; i--) {
      if(bp[i]==pc) {
        PRINTF(L_SYS_EMU,"6805: breakpoint at %04x (count=%d)",pc,count);
        return 0;
        }
      }
    if(count>=max_count) {
      PRINTF(L_SYS_EMU,"max. instruction counter exceeded (count=%d)",count);
      return 2;
      }
    }
}
void c6805::Set ( unsigned char  seg,
unsigned short  ea,
unsigned char  val 
) [protected]

Definition at line 233 of file cpu.c.

References hasWriteHandler, PAGEOFF, cMap::Set(), and WriteHandler().

{
  if(hasWriteHandler) WriteHandler(seg,ea,val);
  unsigned char mapId=mapMap[ea+PAGEOFF(ea,seg)];
  if(!(mapId&0x80)) mapper[mapId&0x7f]->Set(ea,val);
}
void c6805::Set ( unsigned short  ea,
unsigned char  val 
) [protected]

Definition at line 226 of file cpu.c.

References cr, hasWriteHandler, PAGEOFF, cMap::Set(), and WriteHandler().

Referenced by cEmuRom10Core::CoreInitSetup(), cEmuRom3Core::CoreInitSetup(), cEmuRom10Core::CoreUpdateSetup(), ForceSet(), cEmu::GetPkKeys(), cEmu::Init(), cEmuRom10::MathMapHandler(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessEx(), Run(), SetMem(), cN2Prov0101::Stepper(), cEmuRom11::UpdateSetup(), and cEmuRom10::UpdateSetup().

{
  if(hasWriteHandler) WriteHandler(cr,ea,val);
  unsigned char mapId=mapMap[ea+PAGEOFF(ea,cr)];
  if(!(mapId&0x80)) mapper[mapId&0x7f]->Set(ea,val);
}
void c6805::SetExptBase ( unsigned short  base) [protected]

Definition at line 337 of file cpu.c.

{
  exptBase=base;
}
void c6805::SetMem ( unsigned short  addr,
const unsigned char *  data,
int  len,
unsigned char  seg = 0 
) [protected]

Definition at line 247 of file cpu.c.

References Set().

Referenced by cN2Prov0101::Algo(), cEmuRom10Core::CoreUpdateSetup(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cEmuRom10::MathMapHandler(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0501::RunEmu(), cN2Prov0101::RunEmu(), and cEmuRom7::UpdateSetup().

{
  while(len>0) { Set(seg,addr++,*data++); len--; }
}
void c6805::SetPc ( unsigned short  addr,
unsigned char  seg = 0 
) [protected]

Definition at line 263 of file cpu.c.

References ClearExceptions(), cr, and ResetCycles().

Referenced by cN2Prov0101::Algo(), cEmu::GetOpKeys(), cEmu::GetPkKeys(), cEmu::Init(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0101::RomInit(), cN2Prov0501::RunEmu(), and cN2Prov0101::RunEmu().

{
  pc=addr; cr=seg;
  ResetCycles();
  ClearExceptions();
}
void c6805::SetSp ( unsigned short  SpHi,
unsigned short  SpLow 
) [protected]

Definition at line 257 of file cpu.c.

Referenced by cN2Prov0101::Algo(), cEmu::Init(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), cN2Prov0101::ProcessEx(), cN2Prov0101::RomInit(), cN2Prov0501::RunEmu(), and cN2Prov0101::RunEmu().

{
  spHi =sp=SpHi;
  spLow   =SpLow;
}
virtual void c6805::Stepper ( void  ) [protected, pure virtual]

Implemented in cEmuRom3Core, cEmuRom10Core, cN2Prov0101, and cN2Emu.

Referenced by Run().

virtual void c6805::TimerHandler ( unsigned int  num) [inline, protected, virtual]

Reimplemented in cN2Prov0101, and cN2Prov0501.

Definition at line 162 of file cpu.h.

Referenced by AddCycles().

{}
virtual void c6805::WriteHandler ( unsigned char  seg,
unsigned short  ea,
unsigned char &  op 
) [inline, protected, virtual]

Reimplemented in cEmuRom3Core, cEmuRom10Core, and cN2Prov4101.

Definition at line 160 of file cpu.h.

Referenced by Set().

{}

Member Data Documentation

unsigned char c6805::a [protected]

Definition at line 130 of file cpu.h.

Referenced by c6805(), cEmuRom10::MathMapHandler(), cEmu::MathMapHandler(), cN2Prov4101::ProcessBx(), cN2Prov0501::ProcessBx(), cN2Prov0101::ProcessBx(), and Run().

struct c6805::CC c6805::cc [protected]

Referenced by c6805(), cEmu::GetPkKeys(), cEmuRom10Core::ReadHandler(), and Run().

unsigned char c6805::cr [protected]

Definition at line 130 of file cpu.h.

Referenced by c6805(), Get(), PopCr(), Run(), Set(), SetPc(), and cN2Prov4101::WriteHandler().

unsigned char c6805::dr [protected]

Definition at line 130 of file cpu.h.

Referenced by c6805(), Run(), and cN2Prov0101::Stepper().

bool c6805::hasReadHandler [protected]

Definition at line 132 of file cpu.h.

Referenced by c6805(), cEmuRom10Core::cEmuRom10Core(), cEmuRom3Core::cEmuRom3Core(), cN2Prov0101::cN2Prov0101(), and Run().

bool c6805::hasWriteHandler [protected]

Definition at line 132 of file cpu.h.

Referenced by c6805(), cEmuRom10Core::cEmuRom10Core(), cEmuRom3Core::cEmuRom3Core(), cN2Prov4101::cN2Prov4101(), and Set().

cLineBuff* c6805::loglb [protected]

Definition at line 169 of file cpu.h.

Referenced by AddMapper(), c6805(), Run(), cN2Prov0101::Stepper(), and ~c6805().

unsigned char c6805::x [protected]

Definition at line 130 of file cpu.h.

Referenced by c6805(), Run(), and ~c6805().

unsigned char c6805::y [protected]

Definition at line 130 of file cpu.h.

Referenced by c6805(), and Run().

The documentation for this class was generated from the following files:
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